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Product Center

Photonic-Electronic Computing Card
Photonic-Electronic Computing Card

Photonic in-memory computing chip combined with mixed-signal SoC, utilizing photonic-electronic hybrid architecture and 3D co-packaging. Features built-in optical interconnect, high integration, stability, and low power. Enables flexible multi-node systems with native FP8 support.

Photonic-Electronic Computing System

Next-gen all-optical large-scale AI computing system with integrated photonic-electronic cards/modules/clusters. Pioneers photonic-electronic computing architecture, delivering full-scenario, full-stack optical solutions via optical computing, interconnect, and transmission.

Photonic-Electronic Computing Card

Technology Roadmap

Technology Roadmap

Technology Roadmap

Silicon-Photonics PCM Heterogeneous Integration + Crossbar Photonic Matrix
Compact footprint, Easy packaging, High-density integration
Compact footprint, Easy packaging, High-density integration
Zero static power, Rock-solid stable
Zero static power, Rock-solid stable
Fast-switching, Compute-optimized
Fast-switching, Compute-optimized
Compact footprint, Easy packaging, High-density integration
Compact footprint, Easy packaging, High-density integration
Zero static power, Rock-solid stable
Zero static power, Rock-solid stable
Fast-switching, Compute-optimized
Fast-switching, Compute-optimized

Development History

Development History

Development History

Entering the Age of Light-Powered Intelligence
2022-2023
From Concept to Tech Transfer
Founded in Apr 2022. Taped out 25×25 & 50×50 optical computing chips in 2023;
launched 1st-gen co-packaged chip & board demo (optical chip + FPGA), validating product concept.
2024-2025
From Product to Ecosystem
Taped out world’s 1st 128×128 optical computing chip in 2024. Completed algorithm tests & opto-electronic verification in 2025; secured strategic investments from internet leaders and state-owned funds, gaining industry and government recognition.
2026-Future
Light, Scaled
Plan to tape out 512×512 optical chip in 2026, iterate computing cards twice. Performance to surpass electronic counterparts, scaling in cloud AI inference (e.g., large models, data centers), with initial edge-side validation.

News & Updates

News & Updates

News & Updates